The European Union is funding research into the design of future microchips. Glasgow University professor Asen Asenov says developers need new circuit and system design to shrink the size of transistors for more powerful circuits. Glasgow is participating in the Tera-scale Reliable Adaptive Memory Systems (TRAMS) consortium, along with Intel Iberia, Interuniversitair Micro-Elektronica Centrium, and the Universitat Politecnica de Catalunya. “We hope this project will result in new chip design paradigms for building reliable memory systems out of unreliable nanoscale components cheaply and effectively, heralding the era of terascale computing,” Asenov says. TRAMS will focus on next-generation complementary metal-oxide semiconductor transistors and microchips.
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