Researchers from academia and industry have until April 11, 2010, to submit applications for an opportunity to test prototypes of potential future high-performance computing (HPC) petascale systems. The Partnership for Advanced Computing in Europe (PRACE) is making nine different prototypes available, including three prototypes of hybrid clusters. The prototypes are not intended for production work. PRACE, which will give priority to teams focusing on research in areas that are different from the partnership’s research, will publicly release a summary of the applicants’ project purpose and the results achieved during prototype testing. Researchers will be able to use the prototype systems for three months per application. The project will allow PRACE to research petascale prototypes, as well as the scaling and optimization of applications on petascale machines. Selections will be made on May 1.
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Silicon Valley is losing more foreign-born executives, engineers, and scientists due to better opportunities in their native countries, tough U.S. immigration laws, and the high cost of living in California. Meanwhile, the Silicon Valley Index shows that fewer foreign students are pursuing engineering and science degrees in the region. The annual study found that foreign students received 16.6 percent of all degrees awarded in science and engineering programs from local colleges and universities in 2007, down from 18.4 percent in 2003. Harvard Law School senior research associate Vivek Wadhwa says the region is experiencing a massive brain drain. “For the first time, immigrants have better opportunities outside the U.S.,” he says. A lack of work visas also can push foreign talent to leave the United States. Legislation pending in the U.S. Congress would give immigrant entrepreneurs with investment funding a two-year visa.
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University of Illinois researchers have taken several small steps toward developing new parallel programming models to tap the many-core processors of the future. The DeNovo project attempts to define a new and more rigorous way of utilizing shared memory. It is working concurrently with a separate effort to define a deterministic, parallel language primarily based on a parallel version of Java and eventually migrating to a parallel version of C++. The chip project that is nearest to testing is the 1,024-core Rigel processor architecture targeting high density, high throughput computing, which would be programmed through a task-level applications programming interface aimed at chores in imaging, computer vision, physics, and simulations. The Bulk Architecture chip design is testing the notion of atomic transactions.
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