Engineers announced at three recent industry events that they are preparing to deliver chips next year that can accommodate serial data streams running at 25 Gbps to drive next-generation 100 Gbps and 400 Gbps networks. However, they remain uncertain as to how or whether they can support follow-on elements for the terabit networks that modern-day Internet data centers are already calling for. “We are starting to press some physical boundaries such as switching speeds of silicon and traces on printed circuit boards–and all of this is changing the cost dynamics,” says Intel’s Bob Grow. The 25 Gbps Serdes standard unveiled at a meeting of the Optical Internetworking Forum could shrink to just four the number of parallel high-speed channels required for 100 Gbps Ethernet chips. Assuming signal integrity problems can be overcome, the 25 Gbps channels will eventually be employed to construct a new suite of interfaces that will present even more formidable challenges. Experts agree that the next developmental phase will demand unprecedented cooperation between chip, board, connector, and tool manufacturers.
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