Low-power design will be a key theme of the 46th Design Automation Conference (DAC), with Synopsys’ Cary Chin agreeing that “low power is one of the biggest challenges that designers face today.” He notes that leakage power concerns at the 90nm node and below, coupled with demands for greater functionality on portable devices, are driving demand for methods to reduce both static and dynamic power consumption. “At 40nm and below, where leakage power is a dominant factor, designers across most market segments are focused on addressing power through better voltage domain management at the block level and careful management of clock trees through the chip,” says Magma Design Automation’s Dan Blong. MIPS Technologies’ Mark Throndson says designers are following even more drastic strategies to fight advanced node leakage, such as dynamic core shutdown. Barry Pangrle with Mentor Graphics observes that designers are concentrating more on using multiple voltages and multiple voltage domains in their designs because dynamic power is proportional to the voltage squared, and he points out that “in cases where a portion of the design’s functionality isn’t needed, the power can be shut off to further reduce the leakage power.” Leakage power relies greatly on process technology, and Pangrle says that foundries usually have multiple offerings at a given technology node, spanning the spectrum from slower transistors with better leakage power traits to faster transistors that consume more power. Designers also have to contend with the problem of the non-interoperable Common Power Format and Unified Power Format. Blong notes that computer servers are estimated to consume 1.3 percent of the world’s generated electricity by next year, while Pangrle says products are being steered toward better energy efficiency by market forces.

View Full Article

For more information please visit: http://www.cpccci.com